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3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
IDT72V71650
FEATURES:
* * * * * * * * * * * * * * *
DESCRIPTION:
The IDT72V71650 has a non-blocking switch capacity of 1,024 x 1,024 channels at 2.048Mb/s, 2,048 x 2,048 channels at 4.096Mb/s, and 4,096 x 4,096 channels at 8.192Mb/s and 8,192 x 8,192 channels at 16.384Mb/s. With 32 inputs and 32 outputs, programmable per stream control, and a variety of operating modes the IDT72V71650 is designed for the TDM time slot interchange function in either voice or data applications. Some of the main features of the IDT72V71650 are low power 3.3 Volt operation, automatic ST-BUS(R) /GCI sensing, memory block programming, simple microprocessor interface, one cycle direct internal memory accesses, JTAG Test Access Port (TAP) and per stream programmable input offset delay, variable or constant throughput modes, output enable and processor mode. The IDT72V71650 is capable of switching up to 8,192 x 8,192 channels without blocking. Designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data, the device maintains frame integrity in data applications and minimizes throughput delay for voice applications on a per-channel basis.
8K x 8K non-blocking switching at 16.384Mb/s 32 serial input and output streams Accepts data streams at 2.048Mb/s, 4.096Mb/s, 8.192Mb/s or 16.384Mb/s Per-channel Variable Delay Mode for low-latency applications Per-channel Constant Delay Mode for frame integrity applications Automatic identification of ST-BUS(R) and GCI bus interfaces Automatic frame offset delay measurement Per-stream frame delay offset programming Per-channel high-impedance output control Direct microprocessor access to all internal memories Memory block programming for quick setup IEEE-1149.1 (JTAG) Test Port 3.3V Power Supply Available in 144-pin (13mm x 13mm) Plastic Ball Grid Array (PBGA) and 144-pin (20mm x 20mm) Thin Quad Flatpack (TQFP) packages Operating Temperature Range -40C to +85C
FUNCTIONAL BLOCK DIAGRAM
VCC
GND
RESET
ODE
TX0 RX0 RX1
Data Memory
MUX
TX1
Receive Serial Data Streams
Internal Registers
RX31
Connection Memory
Transmit Serial Data Streams
TX15 TX16/OEI0 TX17/OEI1
TX31/OEI15
Timing Unit
Microprocessor Interface
JTAG Port
CLK
FP
FE/HCLK WFPS
DS
CS
R/W
A0-A14
DTA
D0-D15
TMS TDI TCK TDO TRST
5906 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS is a trademark of Mitel Corp.
OCTOBER 2003
DSC-5906/9
2003
1
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT72V71650 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
A1 BALL PAD CORNER
A
CLK RESET ODE RX1 RX4 RX7 TX4 TX7 TX10 TX12 TX14 TX15
B
FP FE/HCLK TMS RX0 TDI RX2 RX3 RX5 RX6 TX0 TX1 TX3 TX2 TX6 TX5 TX9 TX8 TX11 RX11 TX13 RX10 RX8 RX9
C
WFPS
D
TDO
TCK R/W
TRST A0
DS VCC
VCC GND
VCC GND
VCC GND
VCC GND
RX15 VCC
RX14 RX18
RX13 RX17
RX12 RX16
E
CS
F
A1 A2 A3 VCC GND GND GND GND VCC RX21 RX20 RX19 TX16/ OEI0 TX19/ OEI3 TX22/ OEI6 TX24/ OEI8 TX26/ OEI10 TX27/ OEI11
G
A6 A5 A4 VCC GND GND GND GND VCC RX22 TX17 /OEI1 TX20/ OEI4 TX31/ OEI15 TX30/ OEI14 TX29/ OEI13 RX23 TX18/ OEI2 TX21/ OEI5 TX23/ OEI7 TX25/ OEI9 TX28/ OEI12
H
A9 A8 A12 A7 A11 VCC A10 GND GND GND GND VCC
J
A13 VCC VCC D2 VCC VCC RX27
K
NC(1) NC(1) DTA D13 A14 D8 D5 D1 RX30 RX26
L
D15 D11 D12 D9 D10 D6 D7 D3 D4 D0 RX31 RX29 RX28 RX25 RX24
M
D14
1
2
3
4
5
6
7
8
9
10
11
12
5906 drw02
PBGA: 1mm pitch, 13mm x 13mm (BB144-1, order code: BB) TOP VIEW
NOTE: 1. NC = No Connect
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IDT72V71650 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATIONS (CONTINUED)
GND VCC TX15 TX14 TX13 TX12 GND VCC TX11 TX10 TX9 TX8 GND VCC TX7 TX6 TX5 TX4 GND VCC TX3 TX2 TX1 TX0 GND VCC RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 ODE RESET
109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
RX8 RX9 RX10 RX11 RX12 RX13 RX14 RX15 RX16 RX17 RX18 RX19 RX20 RX21 RX22 RX23 GND VCC TX16/OEI0 TX17/OEI1 TX18/OEI2 TX19/OEI3 GND VCC TX20/OEI4 TX21/OEI5 TX22/OEI6 TX23/OEI7 GND VCC TX24/OEI8 TX25/OEI9 TX26/OEI10 TX27/OEI11 GND VCC
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
TX28/OEI12 TX29/OEI13 TX30/OEI14 TX31/OEI15 GND VCC RX24 RX25 RX26 RX27 RX28 RX29 RX30 RX31 GND VCC D0 D1 D2 D3 GND VCC D4 D5 D6 D7 GND VCC D8 D9 D10 D11 GND VCC D12 D13
*
5906 drw03
PIN 1
NOTE: 1. NC = No Connect
GND CLK FP FE/HCLK WFPS TMS TDI TDO TCK TRST DS CS R/W VCC A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 NC(1) NC(1) DTA VCC GND D15 D14
TQFP: 0.50mm pitch, 20mm x 20mm (DA144-1, order code: DA) TOP VIEW
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IDT72V71650 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
SYMBOL NAME A0-14 Address 0 to 14 CLK CS D0-15 DS DTA Clock Chip Select Data Bus 0-15 Data Strobe Data Transfer Acknowledgment I/O DESCRIPTION I These address lines access all internal memories. I I Serial clock for shifting data in/out on the serial data streams. Depending upon the value programmed, this input accepts a 4.096, 8.192 or 16.384 MHz clock. See the Control Register bits on Table 5 for the values. This active LOW input is used by a microprocessor to activate the microprocessor port of IDT72V71650.
I/O These pins are the data bits of the microprocessor port. I This active LOW input works in conjunction with CS to enable the read and write operations and enables the data bus lines (D0-D15). O Indicates that a data bus transfer is complete. When the bus cycle ends, this pin drives HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required to hold a HIGH level when the pin is in high-impedance.
When the WFPS pin is LOW, this pin is the frame measurement input. When the WFPS pin is HIGH, the HCLK (4.096 MHz clock) is required for frame alignment in the wide frame pulse mode (WFPS).(1)
FE/HCLK Frame Evaluation/ HCLK Clock
I
FP
Frame Pulse
I
GND ODE
Ground Output Drive Enable I
When the WFPS pin is LOW, this input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS(R) and GCI specifications. When pin WFPS is HIGH, this pin accepts a negative frame pulse, which conforms to the WFPS format. Ground Rail. This is the output enable control for the TX serial outputs. When the ODE input is LOW and the Output Stand By bit of the Control Register is LOW, all TX outputs are in a high-impedance state. If this input is HIGH, the TX output drivers are enabled. However, each channel may still be put into a high-impedance state by using the per-channel control bit in the Connection Memory. This input puts the IDT72V71650 into a reset state that clears the device internal counters, registers and brings TX0-31 and D0-D15 into a high-impedance state. The RESET pin must be held LOW for a minimum of 20ns to properly reset the device. This input controls the direction of the data bus lines (D0-D15) during a microprocessor access. Serial data input stream. These streams may have a data rate of 2.048Mb/s, 4.096Mb/s, 8.192Mb/s, or 16.384Mb/s, depending upon the value programmed in the Control Register. Provides the clock to the JTAG test logic. JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up when not driven. JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state when JTAG scan is not enabled. JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal pull-up when not driven. Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin is pulled by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW, to ensure that the IDT72V71650 is in the normal functional mode. Serial data output stream. These streams may have a data rate of 2.048Mb/s, 4.096Mb/s, 8.192Mb/s, or 16.384Mb/s, depending upon the value programmed in the Control Register. When all 32 outputs streams are selected via Control Register, these pins are the output streams TX16 to TX31 and may operate at a data rate of 2.048Mb/s, 4.096Mb/s, 8.192Mb/s, or 16.384Mb/s. When output enable function is selected, these pins reflect the active or high-impedance status for the corresponding output stream OEI0-31. +3.3 Volt Power Supply. When 1, enables the wide frame pulse (WFPS) Frame Alignment interface. When 0, the device operates in ST-BUS(R) /GCI mode.(2)
RESET
Device Reset
I
R/W RX0-31 TCK TDI TDO TMS TRST
Read/Write Data Stream Test Clock Test Serial Data In Test Serial Data Out Test Mode Select Test Reset
I I I I O I I
TX0-15
TX Output 0 to 15 (Three-state Outputs)
O O
TX16-31/ TX Output 16 to 31/ OEI0-15 Output Enable Indication 0 to 15 (Three-State Outputs) VCC VCC WFPS Wide Frame Pulse Select
I
NOTES: 1. For compatibility with the IDT72V73273/63 device, this pin should be logic High. 2. For compatibility with the IDT72V73273/63 device, this pin should be logic Low.
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IDT72V71650 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURE RANGE
DESCRIPTION (CONTINUED)
The 32 serial input streams (RX) of the IDT72V71650 can run up to 16.384Mb/s allowing 256 channels per 125s frame. The data rates on the output streams (TX) are identical to those on the input streams (RX). With two main operating modes, Processor Mode and Connection Mode, the IDT72V71650 can easily switch data from incoming serial streams (Data Memory) or from the controlling microprocessor via Connection Memory. As control and status information is critical in data transmission, the Processor Mode is especially useful when there are multiple devices sharing the input and output streams. With data coming from multiple sources and through different paths, data entering the device is often delayed. To handle this problem, the IDT72V71650 has a Frame Evaluation feature to allow individual streams to be offset from the frame pulse in half clock-cycle intervals up to +7.5 clock cycles. The IDT72V71650 also provides a JTAG test access port, memory block programming, a simple microprocessor interface and automatic ST-BUS(R) /GCI sensing to shorten setup time, aid in debugging and ease use of the device without sacrificing capabilities.
setup the device. The IDT72V71650 provides two different interface timing modes, ST-BUS(R) or GCI. The IDT72V71650 automatically detects the presence of an input frame pulse and identifies it as either ST-BUS or GCI. In ST-BUS, when running at 16.384 MHz, data is clocked out on the falling edge and is clocked in on the subsequent rising-edge. At all other data rates, there are two clock cycles per bit and every second falling edge of the master clock marks a bit boundary and the data is clocked in on the rising edge of CLK, three quarters of the way into the bit cell. See Figure 13 for timing. In GCI format, when running at 16.384 MHz, data is clocked out on the rising edge and is clocked in on the subsequent falling edge. At all other data rates, there are two clock cycles per bit and every second rising edge of the master clock marks the bit boundary and data is clocked in on the falling edge of CLK at three quarters of the way into the bit cell. See Figure 14 for timing. INPUT FRAME OFFSET SELECTION Input frame offset selection allows the channel alignment of individual input streams to be offset with respect to the output stream channel alignment. Although all input data comes in at the same speed, delays can be caused by variable path serial backplanes and variable path lengths which may be implemented in large centralized and distributed switching systems. Because data is often delayed, this feature is useful in compensating for the skew between input streams. Each input stream can have its own delay offset value by programming the frame input offset registers (FOR, Table 8). The maximum allowable skew is +7.5 master clock (CLK) periods forward with a resolution of 1/2 clock period, see Table 9. The output frame cannot be adjusted. SERIAL INPUT FRAME ALIGNMENT EVALUATION The IDT72V71650 provides the Frame Evaluation input to determine different data input delays with respect to the frame pulse FP. A measurement cycle is started by setting the Start Frame Evaluation bit of the Control Register LOW for at least one frame. When the Start Frame Evaluation bit in the Control Register is changed from LOW to HIGH, the evaluation starts. Two frames later, the Complete Frame Evaluation bit of the Frame Alignment Register changes from LOW to HIGH to signal that a valid offset measurement is ready to be read from bits 0 to 11 of the Frame Alignment Register. The Start Frame Evaluation bit must be set to zero before a new measurement cycle is started. In ST-BUS (R) mode, the falling edge of the frame measurement signal (Frame Evaluation) is evaluated against the falling edge of the ST-BUS (R) frame pulse. In GCI mode, the rising edge of Frame Evaluation is evaluated against the rising edge of the GCI frame pulse. See Table 7 and Figure 1 for the description of the Frame Alignment Register. MEMORY BLOCK PROGRAMMING The IDT72V71650 provides users with the capability of initializing the entire Connection Memory block in two frames. To set bits 14 and 15 of every Connection Memory location, first program the desired pattern in the Block Programming Data Bits (BPD 1-0), located in bits 7 and 8 of the Control Register. The block programming mode is enabled by setting the Memory Block Program bit of the Control Register HIGH. When the Block Programming Enable bit of the Control Register is set to HIGH, the Block Programming Data will be loaded into the bits 14 and 15 of every Connection Memory location. The other Connection Memory bits (bit 0 to bit 13) are loaded with zeros. When the memory block programming is complete, the device resets the Block Programming Enable, Block Programming Data 1-0 and Memory Block Program bits to zero.
FUNCTIONAL DESCRIPTION
DATA AND CONNECTION MEMORY All data that comes in through the RX inputs go through a serial-to-parallel conversion before being stored into internal Data Memory. The 8 KHz frame pulse (FP) is used to mark the 125s frame boundaries and to sequentially address the input channels in Data Memory. Data output on the TX streams may come from either the serial input streams (Data Memory) or from the microprocessor (Connection Memory). In the case that RX input data is to be output, the addresses in Connection Memory are used to specify a stream and channel of the input. The Connection Memory is setup in such a way that each location corresponds to an output channel for each particular stream. In that way, more than one channel can output the same data. In Processor Mode, the microprocessor writes data to the Connection Memory locations corresponding to the stream and channel that is to be output. The lower half (8 least significant bits) of the Connection Memory is output every frame until the microprocessor changes the data or mode of the channel. By using this Processor Mode capability, the microprocessor can access input and output time-slots on a per-channel basis. The two most significant bits of the Connection Memory are used to control the per-channel mode of the out put streams. Specifically, the MOD1-0 bits are used to select Processor Mode, Constant or Variable delay Mode, and the highimpedance state of output drivers. If the MOD1-0 bits are set to 1-1 accordingly, only that particular output channel (8 bits) will be in the high-impedance state. If however, the ODE input pin is LOW and the Output Standby Bit in the Control Register is LOW, all of the outputs will be in a high-impedance state even if a particular channel in Connection Memory has enabled the output for that channel. In other words, the ODE pin and Output Stand By control bit are master output enables for the device (See Table 3). SERIAL DATA INTERFACE TIMING When a 16.384Mb/s serial data rate is required, the master clock frequency will be running at 16.384 MHz resulting in a single-bit per clock. For all other cases, 2.048Mb/s, 4.096Mb/s, and 8.192Mb/s, the master clock frequency will be twice the data rate on the serial streams, resulting in two clocks per bit. Use Table 5 to determine clock speed and the DR1-0 bits in the Control Register to
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IDT72V71650 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURE RANGE
DELAY THROUGH THE IDT72V71650
The switching of information from the input serial streams to the output serial streams results in a throughput delay. The device can be programmed to perform time-slot interchange functions with different throughput delay capabilities on a per-channel basis. For voice applications, variable throughput delay is best as it ensures minimum delay between input and output data. In wideband data applications, constant throughput delay is best as the frame integrity of the information is maintained through the switch. The delay through the device varies according to the type of throughput delay selected in the MOD bits of the Connection Memory. VARIABLE DELAY MODE (MOD1-0 = 0-0) In this mode, the delay is dependent only on the combination of source and destination channels and is independent of input and output streams. The minimum delay achievable in the IDT72V71650 is three time-slots. If the input channel data is switched to the same output channel (channel n, frame p), it will be output in the following frame (channel n, frame p+1). The same is true if the input channel n is switched to output channel n+1 or n+2. If the input channel n is switched to output channel n+3, n+4,..., the new output data will appear in the same frame. Table 2 shows the possible delays for the IDT72V71650 in Variable Delay mode. CONSTANT DELAY MODE (MOD1-0 = 0-1) In this mode, frame integrity is maintained in all switching configurations by making use of a multiple data memory buffer. Input channel data is written into the data memory buffers during frame n will be read out during frame n+2. In the IDT72V71650, the minimum throughput delay achievable in Constant Delay mode will be one frame plus one channel. See Table 1.
The data in the Control Register consists of the Memory Block Programming bit, the Block Programming Data bits, the Begin Block Programming Enable, the Output Stand By, Start Frame Evaluation, Output Enable Indication, and Data Rate Select bits. As explained in the Memory Block Programming section, the Block Programming Enable begins the programming if the Memory Block Program bit is enabled. This allows the entire Connection Memory block to be programmed with the Block Programming Data bits. If the ODE pin is LOW, the Output Stand By bit enables (if HIGH) or disables (if LOW) all TX output drivers. If the ODE pin is HIGH, the Output Stand By bit is ignored and all TX output drivers are enabled. SOFTWARE RESET The Software Reset serves the same function as the hardware reset. As with the hard reset, the Software Reset must also be set HIGH for 20ns before bringing the Software Reset LOW again for normal operation. Once the Software Reset is LOW, internal registers and other memories may be read or written. During Software Reset, the microprocessor port is still able to read from all internal memories. The only write operation allowed during a Software Reset is to the Software Reset bit in the Control Register to complete the Software Reset. CONNECTION MEMORY CONTROL If the ODE pin and the Output Stand By bit are LOW, all output channels will be in three-state. See Table 3 for detail. If MOD1-0 of the Connection Memory is 1-0 accordingly, the output channel will be in Processor Mode. In this case the lower eight bits of the Connection Memory are output each frame until the MOD1-0 bits are changed. If MOD 1-0 of the Connection Memory are 0-1 accordingly, the channel will be in Constant Delay Mode and bits 12-0 are used to address a location in Data Memory. If MOD1-0 of the Connection Memory are 0-0, the channel will be in Variable Delay Mode and bits 12-0 are used to address a location in Data Memory. If MOD 1-0 of the Connection Memory are 1-1, the channel will be in High-Impedance mode and that channel will be in three-state. OUTPUT ENABLE INDICATION The IDT72V71650 has the capability to indicate the state of the outputs (active) or three-state) by enabling the Output Enable Indication in the Control Register. In the Output Enable Indication mode however, only half of the output streams are available. If this same capability is desired with all 32 streams, this can be accomplished by using two IDT72V71650 or one IDT72V71660 devices. In one device, the All Output Enable bit is set to a one while in the other the All Output Enable is set to zero. In this way, one device acts as the switch and the other as a three-state control device, see Figure 4. It is important to note if the TSI device is programmed for All Output Enable and the Output Enable Indication is also set, the device will be in the All Output Enable mode not Output Enable Indication.
MICROPROCESSOR INTERFACE
The IDT72V71650's microprocessor interface looks like a standard RAM interface to improve integration into a system. With a 15-bit address bus and a 16-bit data bus, reads and writes are mapped directly into Data and Connection Memories and require only one clock cycle to access. By allowing the internal memories to be randomly accessed in one cycle, the controlling microprocessor has more time to manage other peripheral devices and can more easily and quickly gather information and setup the switch paths. Table 4 shows the mapping of the addresses into internal memory blocks. MEMORY MAPPING The address bus on the microprocessor interface selects the internal registers and memories of the IDT72V71650. The two most significant bits of the address select between the registers, Data Memory, and Connection Memory. If A14 and A13 are HIGH, A12-A0 are used to address the Data Memory. If A14 is HIGH and A13 is LOW, A12-A0 are used to address Connection Memory. If A14 is LOW and A13 is HIGH A12-A0 are used to select the Control Register, Frame Alignment Register, and Frame Offset Registers. See Table 4 for mappings. As explained in the Serial Data Interface Timing and Switching Configurations sections, after system power-up, the Control Register should be programmed immediately to establish the desired switching configuration.
INITIALIZATION OF THE IDT72V71650
After power up, the state of the Connection Memory is unknown. As such, the outputs should be put in high-impedance by holding the ODE pin LOW. While the ODE is LOW, the microprocessor can initialize the device by using the Block Programming feature and program the active paths via the microprocessor bus. Once the device is configured, the ODE pin (or Output Stand By bit depending on initialization) can be switched to enable the TSI switch.
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IDT72V71650 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURE RANGE
TABLE 1 -- CONSTANT THROUGHPUT DELAY VALUE
Input Rate 2.048Mb/s 4.096Mb/s 8.192Mb/s 16.384Mb/s Delay for Constant Throughput Delay Mode (m - output channel number) (n - input channel number) 32 + (32 - n) +m time-slots 64 + (64 - n) +m time-slots 128 + (128 - n) +m time-slots 256 + (256 - n) +m time-slots
TABLE 2 -- VARIABLE THROUGHPUT DELAY VALUE
Input Rate 2.048Mb/s 4.096Mb/s 8.192Mb/s 16.384Mb/s Delay for Variable Throughput Delay Mode (m - output channel number; n - input channel number) m n+2 32 - (n-m) time-slots 64 - (n-m) time-slots 128 - (n-m) time-slots 256 - (n-m) time-slots m > n+2 (m-n) time-slots (m-n) time-slots (m-n) time-slots (m-n) time-slots
TABLE 3 -- OUTPUT HIGH-IMPEDANCE CONTROL
Bits MOD1-0 Values in Connection Memory 1 and 1 Any, other than 1 and 1 Any, other than 1 and 1 Any, other than 1 and 1 Any, other than 1 and 1 ODE pin Don't Care 0 0 1 1 OSB bit in Control Register Don't Care 0 1 0 1 Output Status Per-channel High-Impedance High-Impedance Enable Enable Enable
TABLE 4 -- INTERNAL REGISTER AND ADDRESS MEMORY MAPPING
A14
1 1 0 0 0 0 0 0 0 0 0 0
A13
1 0 1 1 1 1 1 1 1 1 1 1
A12
STA4 STA4 0 0 1 1 1 1 1 1 1 1
A11
A10
A9
A8
A7
CH7 CH7 x x x x x x x x x x
A6
CH6 CH6 x x x x x x x x x x
A5
CH5 CH5 x x x x x x x x x x
A4
CH4 CH4 x x x x x x x x x x
A3
CH3 CH3 x x x x x x x x x x
A2
CH2 CH2 x x x x x x x x x x
A1
A0
R/W
R R/W R R/W R/W R/W R/W R/W R/W R/W R/W
Location
Data Memory Connection Memory Control Register Frame Align Register Frame Offset Register 0 Frame Offset Register 1 Frame Offset Register 2 Frame Offset Register 3 Frame Offset Register 4 Frame Offset Register 5 Frame Offset Register 6 Frame Offset Register 7
STA3 STA2 STA3 STA2 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1
STA1 STA0 STA1 STA0 0 1 0 1 0 1 0 1 0 1 x x x x x x x x x x
CH1 CH0 x x x x x x x x x x x x x x x x x x x x
CH1 CH0 R/W
NOTE: Unused STA and CH bits should be set to zero.
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IDT72V71650 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURE RANGE
TABLE 5 -- CONTROL REGISTER (CR) BITS
Reset Value:
15 SRS 14 OEI
0000H.
13 OEPOL 12 AOE 11 0 10 0 9 MBP 8 BPD1 7 BPD0 6 BPE 5 OSB 4 SFE 3 0 2 0 1 DR1 0 DR0
BIT 15 14 13
NAME SRS (Software Reset) OEI (Output Enable Indication) OEPOL (Output Enable Polarity) AOE (All Output Enables) Unused
DESCRIPTION A one will reset the device and have the same effect as the RESET pin. Must be zero for normal operation. When 1, the TX16-31/OEI0-15 pins will be OEI0-15 and reflect the active or high-impedance state of their corresponding output data streams. When 0, this feature is disabled and these pins are used as output data streams TX16-31. When 1, a one on an Output Enable Indication pin denotes an active state on the output data stream; zero on an Output Enable Indication pin denotes high-impedance state. When 0, a one on an Output Enable Indication pin denotes high-impedance and a zero denotes an active state. When 1, TX0-31 will behave as OEI0-31 accordingly. These outputs will reflect the active or high-impedance state of the corresponding output data streams (TX0-31) in another IDT72V71650 if programmed identically. When 0, the TSI operates in the normal switch mode. Must be zero for normal operation.
12
11-10 9 8-7
MBP When 1, the Connection Memory block programming feature is ready for the programming of Connection Memory HIGH bits, bit (Memory Block Program) 14 to bit 15. When 0, this feature is disabled. BPD1-0 (Block Programming Data) BPE (Begin Block Programming Enable) These bits carry the value to be loaded into the Connection Memory block whenever the memory block programming feature is activated. After the Memory Block Program bit in the Control Register is set to 1 and the Block Programming Enable is set to 1, the contents of the bits Block Programming Data1-0 are loaded into bit 15 and 14 of the Connection Memory. Bit 13 to bit 0 of the Connection Memory are set to 0. A zero to one transition of this bit enables the memory block programming function. The Block Programming Enable and Block Programming Data1-0 bits in the Control Register have to be defined in the same write operation. Once the Block Programming Enable bit is set HIGH, the device requires two frames to complete the block programming. After the programming function has finished, the Block Programming Enable, Memory Block Program and Block Programming Data 1-0 bits will be reset to zero by the device to indicate the operation is complete. When ODE = 0 and Output Stand By = 0, the output drivers of the transmit serial streams are in high-impedance mode. When either ODE = 1 or Output Stand By =1 the output serial streams drivers function normally. A zero to one transition in this bit starts the Frame Evaluation procedure. When the Complete Frame Evaluation bit in the Frame Alignment Register changes from zero to one, the evaluation procedure stops. To start another Frame Evaluation cycle, set this bit to zero for at least one frame. Must be zero for normal operation. DR1 0 0 1 1 DR0 0 1 0 1 Data Rate 2.048Mb/s 4.096Mb/s 8.192Mb/s 16.384Mb/s Master Clock 4.096 MHz 8.192 MHz 16.384 MHz 16.384 MHz
6
5 4
OSB (Output Stand By) SFE (Start Frame Evaluation) Unused DR1-0
3-2 1-0
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IDT72V71650 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURE RANGE
TABLE 6 -- CONNECTION MEMORY BITS
15 MOD1 Bit 15, 14 Name MOD1-0 (Switching Mode Selection) 14 MOD0 13 0 12 SAB4 11 SAB3 10 SAB2 9 SAB1 8 SAB0 7 CAB7 6 CAB6 5 CAB5 4 CAB4 3 CAB3 2 CAB2 1 CAB1 0 CAB0
Description MOD1 MOD0 0 0 0 1 1 0 1 1 MODE Variable Delay mode Constant Delay mode Processor mode Output High-impedance
13 12-8 7-0
Unused SAB4-0 (Source Stream Address Bits) CAB7-0 (Source Channel Address Bits)
Must be zero for normal operation. The binary value is the number of the data stream for the source of the connection. The binary value is the number of the channel for the source of the connection.
NOTE: 1. Unused SAB and CAB bits should be set to zero.
9
IDT72V71650 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURE RANGE
TABLE 7 -- FRAME ALIGNMENT REGISTER (FAR) BITS
Reset Value: 15 0 14 0 13 0 0000H. 12 CFE 11 FD11 10 FD10 9 FD9 8 FD8 7 FD7 6 FD6 5 FD5 4 FD4 3 FD3 2 FD2 1 FD1 0 FD0
Bit 15-13 12 11
Name Unused CFE (Complete Frame Evaluation)
Description Must be zero for normal operation. When Complete Frame Evaluation = 1, the Frame Evaluation is completed and bits FD11 to FD0 bits contains a valid frame alignment offset. This bit is reset to zero, when Start Frame Evaluation bit in the Control Register is changed from 1 to 0.
FD11 The falling edge of Frame Evaluation (or rising edge for GCI mode) is sampled during the CLK-HIGH phase (FD11 = 1) or during the CLK-LOW (Frame Delay Bit 11) phase (FD11 = 0). This bit allows the measurement resolution to 1/2 CLK cycle. This bit is reset to zero when the Start Frame Evaluation bit of the Control Register changes from 1 to 0. FD10-0 (Frame Delay Bits) The binary value expressed in these bits refers to the measured input offset value. These bits are reset to zero when the Start Frame Evaluation bit of the Control Register changes from 1 to 0. (FD10 - MSB, FD0 - LSB)
10-0
ST-BUS Frame
CLK
Offset Value
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FE Input
(FD[10:0] = 06H) (FD11 = 0, sample at CLK LOW phase)
GCI Frame
CLK
Offset Value
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FE Input
(FD[10:0] = 09H) (FD11 = 1, sample at CLK HIGH phase)
5906 drw04
Figure 1. Example for Frame Alignment Measurement
10
IDT72V71650 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURE RANGE
TABLE 8 -- FRAME INPUT OFFSET REGISTER (FOR) BITS
Reset Value:0000H for all FOR registers. Register FOR0 Register FOR1 Register FOR2 Register FOR3 Register FOR4 Register FOR5 Register FOR6 Register FOR7 Register 15 OF32 OF72 14 OF31 OF71 13 OF30 OF70 12 DLE3 DLE7 11 OF22 OF62 10 OF21 OF61 9 OF20 OF60 8 DLE2 DLE6 7 OF12 OF52 OF92 6 OF11 OF51 OF91 5 OF10 OF50 OF90 4 DLE1 DLE5 DLE9 3 OF02 OF42 OF82 2 OF01 OF41 OF81 1 OF00 OF40 OF80 0 DLE0 DLE4 DLE8
OF112 OF111 OF110 DLE11 OF102 OF101 OF100 DLE10
OF152 OF151 OF150 DLE15 OF142 OF141 OF140 DLE14 OF132 OF131 OF130 OF192 OF191 OF190 DLE19 OF182 OF181 OF180 DLE18 OF172 OF171 OF170 OF232 OF231 OF230 DLE23 OF222 OF221 OF220 DLE22 OF212 OF211 OF210 OF272 OF271 OF270 DLE27 OF262 OF261 OF260 DLE26 OF252 OF251 OF250 OF312 OF311 OF310 DLE31 OF302 OF301 OF300 DLE30 OF292 OF291 OF290
DLE13 OF122 OF121 OF120 DLE12 DLE17 OD162 OD161 OF160 DLE16 DLE21 OF202 OF201 OF200 DLE20 DLE25 OF242 OF241 OF240 DLE24 DLE29 OF280 OF281 OF280 DLE28
Name(1) OFn2, OFn1, OFn0 (Offset Bits 2, 1 & 0) DLEn
Description These three bits define how long the serial interface receiver takes to recognize and store bit 0 from the RX input pin: i.e., to start a new frame. The input frame offset can be selected to +7.5 clock periods from the point where the external frame pulse input signal is applied to the FP input of the device. See Figure 2. ST-BUS(R) and GCI mode: DLEn = 0, offset is on the clock boundary DLEn = 1, offset is a half clock cycle off of the clock boundary.
NOTE: 1. n denotes an input stream number from 0 to 31.
11
IDT72V71650 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURE RANGE
TABLE 9 -- OFFSET BITS (OFn2, OFn1, OFn0, DLEn) & FRAME DELAY BITS (FD11, FD2-0)
Measurement Result from Input Stream Offset FD11 No clock period shift (Default) + 0.5 clock period shift + 1.0 clock period shift + 1.5 clock period shift + 2.0 clock period shift + 2.5 clock period shift + 3.0 clock period shift + 3.5 clock period shift + 4.0 clock period shift + 4.5 clock period shift +5.0 clock period shift +5.5 clock period shift +6.0 clock period shift +6.5 clock period shift +7.0 clock period shift +7.5 clock period shift 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 FD2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FD1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FD0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 OFn2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 OFn1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 OFn0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DLEn 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Frame Delay Bits Corresponding Offset Bits
) FP (ST-BUS
CLK
RX Stream (16.384 Mb/s) RX Stream (16.384 Mb/s) RX Stream (16.384 Mb/s)
Bit 7
Bit 6
Bit 5
Bit 4
offset = 0, DLE = 0
Bit 7
Bit 6
Bit 5
offset = 1, DLE = 0
Bit 7
Bit 6
Bit 5
Bit 4
offset = 0, DLE = 1
FP (GCI)
CLK RX Stream (16.384 Mb/s) RX Stream (16.384 Mb/s) RX Stream (16.384 Mb/s)
Bit 0
Bit 1
Bit 2
offset = 0, DLE = 0
Bit 0
Bit 1
Bit 2
offset = 1, DLE = 0
Bit 0
Bit 1
Bit 2
5906 drw05
offset = 0, DLE = 1
Figure 2. Examples for Input Offset Delay Timing in 16.384Mb/s mode
12
IDT72V71650 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
FP (ST-BUS)
INDUSTRIAL TEMPERATURE RANGE
CLK
RX Stream
Bit 7
offset = 0, DLE = 0
RX Stream
Bit 7
offset = 1, DLE = 0
RX Stream
Bit 7
offset = 0, DLE = 1
RX Stream
Bit 7
offset = 1, DLE = 1
denotes the 3/4 point of the bit cell
FP (GCI)
CLK
RX Stream
Bit 0
offset = 0, DLE = 0
RX Stream
Bit 0
offset = 1, DLE = 0
RX Stream
Bit 0
offset = 0, DLE = 1
RX Stream
Bit 0
offset = 1, DLE = 1
denotes the 3/4 point of the bit cell
5906 drw06
Figure 2. Examples for Input Offset Delay Timing in 8.192Mb/s, 4.096Mb/s and 2.048Mb/s mode (Continued)
13
IDT72V71650 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURE RANGE
JTAG SUPPORT
The IDT72V71650 JTAG interface conforms to the Boundary-Scan standard IEEE-1149.1. This standard specifies a design-for-testability technique called Boundary-Scan test (BST). The operation of the boundary-scan circuitry is controlled by an external test access port (TAP) Controller. TEST ACCESS PORT (TAP) The Test Access Port (TAP) provides access to the test functions of the IDT72V71650. It consists of three input pins and one output pin. *Test Clock Input (TCK) TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remains independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells concurrently with the operation of the device and without interfering with the on-chip logic. *Test Mode Select Input (TMS) The logic signals received at the TMS input are interpreted by the TAP Controller to control the test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to VCC when it is not driven from an external source. *Test Data Input (TDI) Serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the TMS input. Both registers are described in a subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is internally pulled to VCC when it is not driven from an external source. *Test Data Output (TDO) Depending on the sequence previously applied to the TMS input, the contents of either the instruction register or data register are serially shifted out through the TDO pin on the falling edge of each TCK pulse. When no data is shifted through the boundary scan cells, the TDO driver is set to a high-impedance state.
*Test Reset (TRST) Reset the JTAG scan structure. This pin is internally pulled to VCC when it is not driven from an external source. INSTRUCTION REGISTER In accordance with the IEEE-1149.1 standard, the IDT72V71650 uses public instructions. The IDT72V71650 JTAG interface contains a four-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP Controller is in its shift-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current, and to define the serial test data register path, which is used to shift data between TDI and TDO during data register scanning. See Table 12 below for Instruction decoding. TEST DATA REGISTER As specified in IEEE-1149.1, the IDT72V71650 JTAG Interface contains two test data registers: *The Boundary-Scan register The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the boundary of the IDT72V71650 core logic. *The Bypass Register The Bypass register is a single stage shift register that provides a one-bit path from TDI to TDO. The IDT72V71650 boundary scan register bits are shown in Table 14. Bit 0 is the first bit clocked out. All three-state enable bits are active HIGH. ID CODE REGISTER As specified in IEEE-1149.1, this instruction loads the IDR with the Revision Number, Device ID, and ID Register Indicator Bit. See Table 10.
TABLE 10 -- IDENTIFICATION REGISTER DEFINITIONS
INSTRUCTION FIELD Revision Number (31:28) IDT Device ID (27:12) IDT JEDEC ID (11:1) ID Register Indicator Bit (Bit 0) VALUE 0x0 0x435 0x33 1 DESCRIPTION Reserved for version number Defines IDT part number Allows unique identification of device vendor as IDT Indicates the presence of an ID register
TABLE 11 -- SCAN REGISTER SIZES
REGISTER NAME Instruction (IR) Bypass (BYR) Identification (IDR) Boundary Scan (BSR) BIT SIZE 4 1 32 Note(1)
NOTES: 1. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local IDT sales representative.
14
IDT72V71650 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURE RANGE
TABLE 12 -- SYSTEM INTERFACE PARAMETERS
INSTRUCTION EXTEST BYPASS IDCODE HIGH-Z CLAMP SAMPLE/PRELOAD CODE 0000 1111 0010 0100 0011 0001 DESCRIPTION Forces contents of the boundary scan cells onto the device outputs(1). Places the boundary scan register (BSR) between TDI and TDO. Places the bypass register (BYR) between TDI and TDO. Loads the ID register (IDR) with the vendor ID code and places the register between TDI and TDO. Places the bypass register (BYR) between TDI and TDO. Forces all device output drivers to a High-Z state. Places the bypass register (BYR) between TDI and TDO. Forces contents of the boundary scan cells onto the device outputs. Places the boundary scan register (BSR) between TDI and TDO. SAMPLE allows data from device inputs(2) and outputs(1) to be captured in the boundary scan cells and shifted serially through TDO. PRELOAD allows data to be input serially into the boundary scan cells via the TDI.
RESERVED
All other codes Several combinations are reserved. Do not use other codes than those identified above.
NOTES: 1. Device outputs = All device outputs except TDO. 2. Device inputs = All device inputs except TDI, TMS and TRST.
TABLE 13 -- JTAG AC ELECTRICAL CHARACTERISTICS (1,2,3,4)
SYMBOL tJCYC tJCH tJCL tJR tJF tJRST tJRSR tJCD tJDC tJS tJH PARAMETER JTAG Clock Input Period JTAG Clock High JTAG Clock Low JTAG Clock Rise Time JTAG Clock Fall Time JTAG Reset JTAG Reset Recovery JTAG Data Output JTAG Data Output Hold JTAG Setup JTAG Hold MIN. 100 40 40 50 50 0 15 15 MAX. 3
(1)
UNITS ns ns ns ns ns ns ns ns ns ns ns
3(1) 25
NOTES: 1. Guaranteed by design. 2. 30pF loading on external output signals. 3. Refer to AC Electrical Test Conditions stated earlier in this document. 4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
tJF tJCL TCK
tJCYC tJR tJCH
Device Inputs(1) TDI/TMS tJS Device Outputs(2) TDO tJRSR TRST tJRST
NOTES: 1. Device inputs = All device inputs except TDI, TMS and TRST. 2. Device outputs = All device outputs except TDO.
tJH tJDC
tJCD
5906 drw07
Figure 3. JTAG Timing Specifications
15
IDT72V71650 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURE RANGE
TABLE 14 -- BOUNDARY SCAN REGISTER BITS
Device Pin ODE RESET CLK FP FE(HCLK) WFPS DS CS R/W A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 DTA D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 RX31 RX30 RX29 RX28 RX27 RX26 RX25 RX24 TX31/OEI15 TX30/OEI14 TX29/OEI13 Boundary Scan Bit 0 to bit 168 Input Output Three-State Scan Cell Scan Cell Control 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86
16
Device Pin TX28/OEI12 TX27/OEI11 TX26/OEI10 TX25/OEI9 TX24/OEI8 TX23/OEI7 TX22/OEI6 TX21/OEI5 TX20/OEI4 TX19/OEI3 TX18/OEI2 TX17/OEI1 TX16/OEI0 RX23 RX22 RX21 RX20 RX19 RX18 RX17 RX16 RX15 RX14 RX13 RX12 RX11 RX10 RX9 RX8 TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0
Boundary Scan Bit 0 to bit 168 Input Output Three-State Scan Cell Scan Cell Control 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
IDT72V71650 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VCC Vi IO TS PD Parameter Supply Voltage Voltage on Digital Inputs Current at Digital Outputs Storage Temperature Package Power Dissapation Min. -0.5 GND -0.3 -50 -55 Max. +4.0 VCC +0.3 50 +125 2 Unit V V mA C W
RECOMMENDED OPERATING CONDITIONS(1)
Symbol VCC VIH VIL TOP Parameter Positive Supply Input HIGH Voltage Input LOW Voltage Operating Temperature Industrial Min. 3.0 2.0 -0.3 -40 Typ. 3.3 25 Max. 3.6 VCC 0.8 +85 Unit V V V C
NOTE: 1. Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
NOTE: 1. Voltages are with respect to Ground unless otherwise stated.
DC ELECTRICAL CHARACTERISTICS
Symbol ICC
(2)
Parameter Supply Current @ 2.048Mb/s @ 4.096Mb/s @ 8.192Mb/s @ 16.384Mb/s
Min. 2.4 -
Typ. -
Max. 60 80 90 95 60 60 0.4
Units mA mA mA mA A A V V
IIL(3,4) IOZ
(3,4)
Input Leakage (input pins) High-impedance Leakage Output HIGH Voltage Output LOW Voltage
VOH(5) VOL(6)
NOTES: 1. Voltages are with respect to ground (GND) unless otherwise stated. 2. Outputs unloaded. 3. 0 V VCC. 4. Maximum leakage on pins (output or I/O pins in high-impedance state) is over an applied voltage (V). 5. IOH = 10 mA. 6. IOL = 10 mA.
17
IDT72V71650 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS - TIMING PARAMETER MEASUREMENT VOLTAGE LEVELS
Symbol VTT VHM VLM tR, tF Rating TTL Threshold TTL Rise/Fall Threshold Voltage HIGH TTL Rise/Fall Threshold Voltage LOW Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels CL
(1)
Level 1.5 2.0 0.8 1
Unit V V V V ns V V
Output Load Input Capacitance
150 8
pF pF
Cin(2)
NOTES: 1. JTAG CL is 30 pF. 2. For 144 TQFP
3.3v
VDD 50
330 D.U.T.
I/O
Z0 = 50
5906 drw08
510
30pF*
5906 Drw09
Figure 4. Output Load
Figure 5. Output Load
6
tSOD (Typical, ns)
5 4 3 2 1
Not
Yet
Cha
rac
teri
zed
200
5906 drw10
20 30 50
80 100 Capacitance (pF)
Figure 6. Lumped Capacitive Load, Typical Derating
18
IDT72V71650 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS - FRAME PULSE AND CLOCK
Symbol tFPW Parameter Frame Pulse Width (ST-BUS(R), GCI) Bit rate = 2.048Mb/s Bit rate = 4.096Mb/s Bit rate = 8.192Mb/s or 16.384Mb/s Frame Pulse Setup time before CLK falling (ST-BUS(R) or GCI) Frame Pulse Hold Time from CLK falling (ST-BUS(R) or GCI) CLK Period Bit rate = 2.048Mb/s Bit rate = 4.096Mb/s Bit rate = 8.192Mb/s or 16.384Mb/s CLK Pulse Width HIGH Bit rate = 2.048Mb/s Bit rate = 4.096Mb/s Bit rate = 8.192Mb/s or 16.384Mb/s CLK Pulse Width LOW Bit rate = 2.048Mb/s Bit rate = 4.096Mb/s Bit rate = 8.192Mb/s or 16.384Mb/s Wide Frame Pulse Width HCLK = 4.096Mb/s Frame Pulse Setup Time before HCLK @ 4.096 MHz falling Frame Pulse Hold Time from HCLK @ 4.096 MHz falling HCLK Period @ 4.096 MHz HCLK Pulse Width HIGH @ 4.096Mb/s HCLK Pulse Width LOW @ 4.096Mb/s HCLK Rise/Fall Time Delay between falling edge of HCLK and falling edge of CLK 50 50 190 110 110 -10 Min. 26 26 26 5 10 190 110 55 85 50 20 85 50 20 Typ. 244 122 61 122 61 30 122 61 30 244 244 122 122 150 150 300 150 150 10 10 Max. 295 145 65 300 150 70 150 75 40 150 75 40 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tFPS tFPH tCP
tCH
tCL
tHFPW tHFPS tHFPH tHCP tHCH tHCL tHr, tHf tDIF
19
IDT72V71650 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
tODE(1)
INDUSTRIAL TEMPERATURE RANGE
RESET
tZR tRZ tRS
TX
tRZ
tODELZ
ODE
5906 drw11
NOTE: 1. To guarantee TX outputs remain in high-impedance.
Figure 7. RESET and ODE Timing
C32i
(ST-BUS mode)
C32i
(GCI mode)
tSOD tCHZ
TX
VALID DATA
tCLZ
ODE
tODEA tODELZ
tODEHZ
TX
tSIH
VALID DATA
5906 drw12
TX
VALID DATA
5906 drw13
Figure 8. Serial Output and External Control
Figure 9. Output Driver Enable (ODE)
20
IDT72V71650 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS - MICROPROCESSOR INTERFACE TIMING
Symbol tCSS tRWS tADS tCSH tRWH tADH tDDR tDHR tDSW tSWD tDHW tAKD Parameter CS Setup from DS falling R/W Setup from DS falling Address Setup from DS falling CS Hold after DS rising R/W Hold after DS Rising Address Hold after DS Rising Data Setup from DTA LOW on Read Data Hold on Read Data Setup on Write (Register Write) Valid Data Delay on Write (Connection Memory Write) Data Hold on Write Acknowledgment Delay: Reading/Writing Registers Reading/Writing Memory Min. 0 3 2 0 3 2 1 10 10 5 Typ. 15 Max. 25 0 32 345 200 120 6 20 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
@ 2.048Mb/s @ 4.096Mb/s @ 8.192Mb/s or 16.384Mb/s
tAKH tDSS
Acknowledgment Hold Time Data Strobe Setup Time
21
IDT72V71650 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURE RANGE
CLK GCI
CLK ST-BUS
tDSS
DS
tCSH tCSS
CS
tRWS
R/W
tRWH
tADS
A0-A11 VALID ADDRESS
tADH
tDHR
D0-D15 READ VALID READ DATA
tSWD
D0-D15 WRITE
tDSW
tDHW
VALID WRITE DATA
tDDR
DTA
NOTE: 1. For quick microprocessor access tDSS must be met. In this case tAKD = tAKD (max) - CLK (period) tDSS.
tAKD
tAKH
5906 drw14
Figure 10. Motorola Non-Multiplexed Bus Timing
22
tFPW tCH tCL tr tf
FP
tFPS
tFPH
tCP tCHZ
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CLK
tSOD
TX
Bit 7
tCLZ tOEI
tOEI
OEI(1)
OEI(2) tOEI
5906 drw15
tOEI
IDT72V71650 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
NOTES: 1. When Output Enable Polarity = 1, Output Enable Indication is HIGH when TX is active and LOW when TX is in three-state. 2. When Output Enable Polarity = 0, Output Enable Indication is LOW when TX is active and HIGH when TX is in three-state.
Figure 11. Output Enable Indicator Timing (8 Mb/s ST-BUS(R) )
23 INDUSTRIAL TEMPERATURE RANGE
IDT72V71650 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS -- SERIAL STREAM (ST-BUS(R) and GCI)
Symbol tSIS tSIH tSOD tCHZ tCLZ tODE tODEHZ tODELZ tOEI tRZ tZR tRS tODEA Parameter RX Setup Time RX Hold Time Clock to Valid Data Clock to High-Z Clock to Low-Z Output Driver Enable to Reset High Output Driver Enable (ODE) Delay Output Driver Enable (ODE) to Low-Z Output Enable Indicator Active to High-Z on Master Reset High-Z to Active on Master Reset Reset pulse width Output Drive Enable to Active Min. 4 8 8 3 5 5 8 20 6 Typ. Max. 20 9 9 20 12 12 16 Units ns ns ns ns ns ns ns ns ns ns ns ns ns
24
tHFPW tHFPH
tHFPS
FP
tCH tCL
tCP
CLK
tDIF tHCL
tr
tf
tHCP tHCH
HCLK4.096 MHz
tSOD
Bit 7 Bit 6 Bit 4 Bit 3 Bit 5 Bit 2
tHr
Bit 1
tHf
Bit 0
IDT72V71650 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
TX 8 Mb/s
Bit 1
Bit 0
tSIS tSIH
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
RX 8 Mb/s
Bit 1
Bit 0
Bit 2
Bit 1
Bit 0
5906 drw16
25
Figure 12. WFPS Timing
INDUSTRIAL TEMPERATURE RANGE
FP tFPH tCH tSOD tCP
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7
tFPW
tr tCL
tf
tFPS
CLK
TX 16 Mb/s tSIS
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 2
Bit 1
Bit 0
tSIH
Bit 7
RX 16 Mb/s
Bit 2
Bit 1
Bit 0
FP tFPH tCH tSOD tCP
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
tFPW
tFPS tCL
tr
tf
CLK
TX 8 Mb/s tSIS
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Bit 1
Bit 0
Bit 0
Bit 7
tSIH
Bit 1 Bit 0
IDT72V71650 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
RX 8 Mb/s
Bit 1
Bit 0
FP tFPH tCH tCL tCP
Bit 7 Bit 6 Bit 5
tFPW
tFPS
CLK tSOD
26
tSIS
Bit 7 Bit 6
TX 4 Mb/s tSIH
Bit 0
Bit 4
Bit 3
RX 4 Mb/s
Bit 0
Bit 5
Bit 4
FP tFPH
tFPW
tFPS
tCL
tCH
CLK tSOD
Bit 7
tCP
Bit 6 Bit 5
TX 2 Mb/s
Bit 0
tSIS
Bit 7
tSIH
Bit 6
5906 drw17
RX 2 Mb/s
Bit 0
NOTE:
1. @ 2.048Mb/s mode, last channel = ch 31, @ 4.096Mb/s mode, last channel = ch 63, @ 8.192Mb/s mode, last channel = ch 127. @ 16.384Mb/s mode, last channel = ch 255.
INDUSTRIAL TEMPERATURE RANGE
Figure 13. Serial Interface Timing (ST-BUS Style)
tFPW tFPH tCH tCP
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
FP tCL
tr
tf
tFPS
CLK
tSOD
TX 16 Mb/s tSIH
Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6
Bit 5
Bit 6
Bit 7
tSIS
Bit 0
RX 16 Mb/s tSOD
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6
Bit 6
Bit 7
Bit 7
TX 8 Mb/s tSIS
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5
Bit 6
Bit 7
Bit 7
tSIH
Bit 6 Bit 7
RX 8 Mb/s
Bit 6
Bit 7
tFPW tFPS tCH tSOD tCP
Bit 0 Bit 1 Bit 2 Bit 3
IDT72V71650 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 8,192 x 8,192
FP tCL
tFPS
CLK
TX 4 Mb/s tSIS
Bit 0 Bit 1
Bit 7
tSIH
Bit 2 Bit 3
RX 4 Mb/s
Bit 7
27
tFPW tFPS tFPH tCH tCL tSOD
Bit 0
FP
CLK
tCP
Bit 1
TX 2 Mb/s tSIS tSIH
Bit 0
Bit 7
RX 2 Mb/s
Bit 7
Bit 1
5906 drw18
NOTE:
1. @ 2.048Mb/s mode, last channel = ch 31, @ 4.096Mb/s mode, last channel = ch 63, @ 8.192Mb/s mode, last channel = ch 127. @ 16.384Mb/s mode, last channel = ch 255.
INDUSTRIAL TEMPERATURE RANGE
Figure 14 Serial Interface Timing (GCI Style)
ORDERING INFORMATION
IDT XXXXXX Device Type XX Package X Process/ Temperature Range BLANK Commercial (-40C to +85C)
DA BB
Thin Quad Flatpacks (TQFP, DA144-1) Plastic Ball Grid Array (PBGA, BB144-1)
72V71650
8,192 x 8,1923.3V Time Slot Interchange Digital Switch
5906 drw19
DATASHEET DOCUMENT HISTORY
08/14/2001 09/24/2001 12/19/2001 12/21/2001 03/26/2002 08/02/2002 05/24/2003 10/10/2003 pgs. 3, 18, 19, 21, 22, 24 and 25. pgs. 2, 3, 11, 19, 21, 24 and 25. pgs. 1-6, 8, 10-19, 20-21 and 23-27. pgs. 1, 5, 6, 14-19 and 24. pgs. 17 and 18. pg. 8 pg. 18. pg. 1 and 4. CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
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for Tech Support: 408-330-1753 email:TELECOMhelp@idt.com

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